Problem s VHDL – Číslicová technika – Fórum – Programujte.com

Zdravím, mám tento kod (jedná se o přepínač):

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity prepinac is

    Port ( VSTUP1:   in    STD_LOGIC_VECTOR (6 downto 0);

	 		  VSTUP2: 	in 	STD_LOGIC_VECTOR (6 downto 0);

			  VYBER:		in 	STD_LOGIC;

			  VYSTUP:   out   STD_LOGIC_VECTOR (6 downto 0));

end prepinac;



architecture arch_prepinac of prepinac is



begin



	if (VYBER = '1') then 

		VYSTUP <= VSTUP2;

	else 

		VYSTUP <= VSTUP1;

	end if;



end arch_prepinac;

ISE Auto-Make Log File

-----------------------



Updating: Check Syntax



Starting: 'exewrap @__prepinac_vhd2sprj_exewrap.rsp'





Creating TCL Process

Done: completed successfully.



Starting: 'exewrap -mode pipe -tapkeep -command C:/xilinx_webpack/bin/nt/xst.exe -ifn prepinac.xst -ofn prepinac.stx'





Starting: 'C:/xilinx_webpack/bin/nt/xst.exe -ifn prepinac.xst -ofn prepinac.stx '





Release  - xst E.33

Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

--> Parameter TMPDIR set to .

CPU : 0.00 / 0.03 s | Elapsed : 0.00 / 0.00 s

 

--> Parameter overwrite set to YES

CPU : 0.00 / 0.03 s | Elapsed : 0.00 / 0.00 s

 

--> Compiling vhdl file D:/WebPack_projekty/garaz/prepinac.vhd in Library work.

ERROR:HDLParsers:163 - D:/WebPack_projekty/garaz/prepinac.vhd Line 17. Unexpected symbol read: IF.

CPU : 0.02 / 0.05 s | Elapsed : 0.00 / 0.00 s

 

--> 

EXEWRAP detected a return code of '1' from program 'C:/xilinx_webpack/bin/nt/xst.exe'



Done: failed with exit code: 0001.

Pokud je mi známo IF THEN je možno použít jen v procesu, použijte CASE WHEN