Ahojte, mám za úlohu vytvoriť opis správania a štruktúry 4 bitového počítadla nahor/nadol. Ak povoľovací vstup C je na 1 sa obsah počítadla inkrementuje/dekrementuje. Ak Up = 1 tak počíta nahor inak nadol.
Ak by bol niekto taký dobrý a pozrel sa mi na kód a povedal mi kde mám chybu bol by som mu vďačný.
#include "systemc.h"
SC_MODULE(obvod_NEG) {
sc_in<sc_logic> in1;
sc_in<sc_logic> in2;
sc_out<sc_logic> n_in1;
sc_out<sc_logic> n_in2;
void neg_process(){
n_in1.write(~(in1.read()));
n_in2.write(~(in2.read()));
}
SC_CTOR(obvod_NEG){
SC_METHOD(neg_process);
sensitive << in1;
sensitive << in2;
}
};
SC_MODULE_EXPORT(obvod_NEG);
SC_MODULE(obvod_NEG1) {
sc_in<sc_logic> in1;
sc_out<sc_logic> n_in1;
void neg_process(){
n_in1.write(~(in1.read()));
}
SC_CTOR(obvod_NEG1){
SC_METHOD(neg_process);
sensitive << in1;
}
};
SC_MODULE_EXPORT(obvod_NEG1);
/*SC_MODULE(prirad)
{
sc_in<sc_logic> in1;
sc_out<sc_logic> out1;
void prirad_process(){
out1.write( in1.read());
}
SC_CTOR(prirad){
SC_METHOD(prirad_process);
sensitive << in1;
}
};
SC_MODULE_EXPORT(prirad);*/
SC_MODULE(obvod_AND6)
{
sc_in<sc_logic> in1,in2,in3,in4,in5,in6;
sc_out<sc_logic> out1;
void and6_process(){
out1.write( ( in1.read() & in2.read() & in3.read() & in4.read() & in5.read() &in6.read() ) );
}
SC_CTOR(obvod_AND6)
{
SC_METHOD(and6_process);
sensitive << in1;
sensitive << in2;
sensitive << in3;
sensitive << in4;
sensitive << in5;
sensitive << in6;
}
};
SC_MODULE_EXPORT(obvod_AND6);
SC_MODULE(obvod_AND5) {
sc_in<sc_logic> in1, in2, in3, in4,in5;
sc_out<sc_logic> out1;
void and5_process(){
out1.write( ( in1.read() & in2.read() & in3.read() & in4.read() & in5.read()) );
}
SC_CTOR(obvod_AND5){
SC_METHOD(and5_process);
sensitive << in1 << in2 << in3 << in4 << in5;
}
};
SC_MODULE_EXPORT(obvod_AND5);
SC_MODULE(obvod_AND4) {
sc_in<sc_logic> in1, in2, in3, in4;
sc_out<sc_logic> out1;
void and4_process(){
out1.write( ( in1.read() & in2.read() & in3.read() & in4.read() ) );
}
SC_CTOR(obvod_AND4){
SC_METHOD(and4_process);
sensitive << in1 << in2 << in3 << in4;
}
};
SC_MODULE_EXPORT(obvod_AND4);
SC_MODULE(obvod_AND3) {
sc_in<sc_logic> in1, in2, in3;
sc_out<sc_logic> out1;
void and3_process(){
out1.write( ( in1.read() & in2.read() & in3.read() ) );
}
SC_CTOR(obvod_AND3){
SC_METHOD(and3_process);
sensitive << in1 << in2 << in3;
}
};
SC_MODULE_EXPORT(obvod_AND3);
SC_MODULE(obvod_OR2){
sc_in<sc_logic> in1,in2;
sc_out<sc_logic> out1;
void or2_process(){
out1.write( (in1.read() | in2.read() ) );
}
SC_CTOR(obvod_OR2){
SC_METHOD(or2_process);
sensitive << in1 << in2;
}
};
SC_MODULE_EXPORT(obvod_OR2);
/*SC_MODULE (jkff)
{
sc_in<bool> j, k;
sc_inout<bool> q;
//sc_in<bool> clk;
sc_in_clk clk;
void jk_flop ();
SC_CTOR (jkff) {
SC_METHOD (jk_flop);
sensitive_pos << clk;
}
};
void jkff::jk_flop()
{
sc_uint<2> temp;
temp[1] = j.read( );
temp[0] = k.read( );
switch(temp) {
case 0x1: q.write(0);
break;
case 0x2: q.write(1);
break;
case 0x3:
q.write(!q.read());
break;
default: break;
}
};*/
/*SC_MODULE (jkff)
{
sc_in<bool> j, k;
sc_inout<bool> q, qn;
//sc_in<bool> clk;
sc_in_clk clk;
void jk_flop (){
sc_uint<2> temp;
temp[1] = j.read();
temp[0] = k.read();
switch(temp) {
case 0x1: q.write(0);
break;
case 0x2: q.write(1);
break;
case 0x3:
q.write(~q.read());
break;
default: break;
}
}
SC_CTOR (jkff) {
SC_THREAD (jk_flop);
sensitive_pos << clk;
}
};
SC_MODULE_EXPORT(jkff);*/
SC_MODULE (jkff) {
sc_in<sc_logic> j, k;
sc_in_clk clk;
sc_out<sc_logic> q;
sc_out<sc_logic> qn;
void do_jk_flop ();
SC_CTOR (jkff) {
SC_METHOD (do_jk_flop);
sensitive_pos << clk;
q.initialize((sc_logic)0);
qn.initialize((sc_logic)1);
}
};
void jkff::do_jk_flop() {
if(j.read() == ((sc_logic)1) && k.read() == ((sc_logic)0)) {
q.write((sc_logic)1);
qn.write((sc_logic)0);
}
else if(j.read() == ((sc_logic)0) && k.read() == ((sc_logic)1)) {
q.write((sc_logic)0);
qn.write((sc_logic)1);
}
else if(j.read() == ((sc_logic)1) && k.read() == ((sc_logic)1)) {
q.write(qn);
qn.write(q);
}
else {
q.write(q);
qn.write(qn);
}
}
SC_MODULE(obvod_struktura){
sc_in_clk clk;
sc_in<sc_logic> c, up;
sc_out<sc_logic> vystup1, vystup2, vystup3, vystup4, cout;
//sc_out<sc_logic> vystup1n, vystup2n,vystup3n,vystup4n;
//sc_out<sc_logic> out9;
// prirad prirad1;
obvod_NEG oneg;
obvod_NEG1 oneg1;
obvod_AND3 oand31;
obvod_AND3 oand32;
obvod_AND4 oand41;
obvod_AND4 oand42;
obvod_AND5 oand51;
obvod_AND5 oand52;
obvod_AND6 oand61;
obvod_AND6 oand62;
obvod_OR2 oor21;
obvod_OR2 oor22;
obvod_OR2 oor23;
obvod_OR2 oor24;
jkff jkff1;
jkff jkff2;
jkff jkff3;
jkff jkff4;
jkff jkff5;
sc_signal<sc_logic> d[5], dneg[5];
sc_signal<sc_logic> j[5], k[5];
sc_signal<sc_logic> cneg, upn;
sc_signal<sc_logic> pom1, pom2, pom3, pom4, pom5, pom6, pom7, pom8, pom9;
sc_signal<sc_logic> pom11,pom12,pom13, pom14, pom15, pom16;
void obvod_process_struktura(){
vystup1 = d[0];
vystup2 = d[1];
vystup3 = d[2];
vystup4 = d[3];
cout = d[4];
}
SC_CTOR(obvod_struktura) : oneg ("oneg"), oneg1 ("oneg1"), oand31 ("oand31"), oand32 ("oand32"), oand41 ("oand41"), oand42 ("oand42"), oand51 ("oand51"), oand52 ("oand52"), oand61 ("oand61"), oand62 ("oand62"), oor21 ("oor21"), oor22 ("oor22"), oor23 ("oor23"), oor24 ("oor24"), jkff1 ("jkff1"), jkff2 ("jkff2"), jkff3 ("jkff3"), jkff4 ("jkff4"), jkff5 ("jkff5")
{
//negacie
oneg.in1(up);
oneg.in2(c);
oneg.n_in1(upn);
oneg.n_in2(cneg);
//stage1
oand31.in1(c);
oand31.in2(upn);
oand31.in3(dneg[3]);
oand31.out1(pom5);
oand32.in1(c);
oand32.in2(up);
oand32.in3(d[3]);
oand32.out1(pom6);
oand41.in1(c);
oand41.in2(upn);
oand41.in3(dneg[2]);
oand41.in4(dneg[3]);
oand41.out1(pom3);
oand42.in1(c);
oand42.in2(up);
oand42.in3(d[2]);
oand42.in4(d[3]);
oand42.out1(pom4);
oand51.in1(c);
oand51.in2(upn);
oand51.in3(dneg[1]);
oand51.in4(dneg[2]);
oand51.in5(dneg[3]);
oand51.out1(pom1);
oand52.in1(c);
oand52.in2(up);
oand52.in3(d[1]);
oand52.in4(d[2]);
oand52.in5(d[3]);
oand52.out1(pom2);
oand61.in1(c);
oand61.in2(upn);
oand61.in3(dneg[0]);
oand61.in4(dneg[1]);
oand61.in5(dneg[2]);
oand61.in6(dneg[3]);
oand61.out1(pom7);
oand62.in1(c);
oand62.in2(up);
oand62.in3(d[0]);
oand62.in4(d[1]);
oand62.in5(d[2]);
oand62.in6(d[3]);
oand62.out1(pom8);
// prirad1.in1(c);
// prirad1.out1(pom9);
pom9 = (sc_logic)c;
//dorobit posledny signal!!!! -> hotovo?
//stage2
oor21.in1(pom1);
oor21.in2(pom2);
oor21.out1(pom11);
oor22.in1(pom3);
oor22.in2(pom4);
oor22.out1(pom12);
oor23.in1(pom5);
oor23.in2(pom6);
oor23.out1(pom13);
oor24.in1(pom7);
oor24.in2(pom8);
oor24.out1(pom14);
pom15 = (sc_logic)pom9;
jkff1.j(pom11);
jkff1.k(pom11);
jkff1.clk(clk);
jkff1.q(d[0]);
jkff1.qn(dneg[0]);
jkff2.j(pom12);
jkff2.k(pom12);
jkff2.clk(clk);
jkff2.q(d[1]);
jkff2.qn(dneg[1]);
jkff3.j(pom13);
jkff3.k(pom13);
jkff3.clk(clk);
jkff3.q(d[2]);
jkff3.qn(dneg[2]);
jkff4.j(pom15);
jkff4.k(pom15);
jkff4.clk(clk);
jkff4.q(d[3]);
jkff4.qn(dneg[3]);
oneg1.in1(pom14);
oneg1.n_in1(pom16);
jkff5.j(pom14);
jkff5.k(pom16);
jkff5.clk(clk);
jkff5.q(d[4]);
jkff5.qn(dneg[4]);
SC_METHOD(obvod_process_struktura);
sensitive << d[0];
sensitive << d[1];
sensitive << d[2];
sensitive << d[3];
sensitive << d[4];
sensitive << dneg[0];
sensitive << dneg[1];
sensitive << dneg[2];
sensitive << dneg[3];
sensitive << dneg[4];
}
};
SC_MODULE_EXPORT(obvod_struktura);
SC_MODULE(obvod_spravanie){
sc_in_clk CLK;
sc_in<sc_logic> c,up;
sc_out<sc_logic> cout;
sc_out <sc_bv<4> > output;
sc_out <sc_logic> vystup1, vystup2, vystup3, vystup4;
void do_counter(){
while(true){
if(c == (sc_logic)1 && up == (sc_logic)1){
wait(5,SC_NS);
switch( (output.read()).to_uint()){
case 0: output="0001"; break;
case 1: output="0010"; break;
case 2: output="0011"; break;
case 3: output="0100"; break;
case 4: output="0101"; break;
case 5: output="0110"; break;
case 6: output="0111"; break;
case 7: output="1000"; break;
case 8: output="1001"; break;
case 9: output="1010"; break;
case 10: output="1011"; break;
case 11: output="1100"; break;
case 12: output="1101"; break;
case 13: output="1110"; break;
case 14: output="1111"; cout = (sc_logic)1; break;
case 15: output="0000"; cout = (sc_logic)0; break;
}
}
if(c == (sc_logic)1 && up == (sc_logic)0){
switch((output.read()).to_uint()){
case 0: output="1111"; cout = (sc_logic)1; break;
case 1: output="0000"; cout = (sc_logic)0;break;
case 2: output="0001"; break;
case 3: output="0010"; break;
case 4: output="0011"; break;
case 5: output="0100"; break;
case 6: output="0101"; break;
case 7: output="0110"; break;
case 8: output="0111"; break;
case 9: output="1000"; break;
case 10: output="1001"; break;
case 11: output="1010"; break;
case 12: output="1011"; break;
case 13: output="1100"; break;
case 14: output="1101"; break;
case 15: output="1110"; break;
}
}
}
wait();
}
SC_CTOR(obvod_spravanie){
output.initialize("0000");
cout.initialize((sc_logic)0);
SC_THREAD(do_counter);
sensitive_neg << CLK;
}
};
SC_MODULE_EXPORT(obvod_spravanie);
SC_MODULE(en_clock){
sc_in_clk CLK;
sc_out <sc_logic> clock;
void do_clock(){
if(CLK == true){
clock = (sc_logic)1;
} else {
clock = (sc_logic)0;
}
}
SC_CTOR(en_clock) {
SC_METHOD(do_clock);
sensitive << CLK;
}
};
SC_MODULE(testbench_obvod){
sc_clock CLK;
sc_signal<sc_logic> c, up, vystup1, vystup2, vystup3, vystup4, cout, clock, cout_bhv;
sc_signal<sc_bv<4> > output;
//obvod_spravanie DUT1;
obvod_struktura DUT2;
en_clock CLOCK;
void do_test(){
while (true){
c=(sc_logic)1;
wait(50,SC_NS);
up=(sc_logic)1;
wait(210,SC_NS);
up=(sc_logic)0;
wait(500,SC_NS);
}
}
SC_CTOR(testbench_obvod):
DUT1 ("DUT1"),
DUT2 ("DUT2"),
CLOCK("CLOCK"),
CLK("CLK", 20, SC_NS, 0.5, 0.0, SC_NS, true)
{
CLOCK.CLK(CLK.signal());
CLOCK.clock(clock);
DUT1.c(c);
DUT1.up(up);
DUT1.CLK(CLK.signal());
DUT1.cout(cout_bhv);
DUT1.output(output);
DUT2.c(c);
DUT2.up(up);
DUT2.clk(CLK.signal());
DUT2.vystup1(vystup1);
DUT2.vystup2(vystup2);
DUT2.vystup3(vystup3);
DUT2.vystup4(vystup4);
DUT2.cout(cout);
SC_THREAD(do_test);
}
};
SC_MODULE_EXPORT(testbench_obvod);